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?2008 integrated device technology, inc. july 2008 dsc 5678/6 1 ? functional block diagram ? data input, address, byte enable and control registers ? self-timed write allows fast cycle time separate byte controls for multiplexed bus and bus matching compatibility dual cycle deselect (dcd) for pipelined output mode 2.5v (100mv) power supply for core lvttl compatible, selectable 3.3v (150mv) or 2.5v (100mv) power supply for i/os and control signals on each port includes jtag functionality industrial temperature range (-40c to +85c) is available at 133mhz available in a 256-pin ball grid array (bga) high-speed 2.5v 512k x 36 synchronous dual-port static ram with 3.3v or 2.5v interface idt70t3539m repeat r a 0r cnten r ads r dout0-8_r dout9-17_r i/o 0r -i/o 35r din_r addr_r oe r be r be 2r be 1r be 0r r/ w r ce 0r ce 1r 1 0 1/0 ft /pipe r 1a 0a 1b 0b 1c 0c 1d 0d dcba clk r , counter/ address reg. dcba 0/1 0d 1d 0c 1c 0b 1b 0a 1a b w 2 r b w 1 r b w 0 r ft /pipe r counter/ address reg. cnten l ads l repeat l dout0-8_l dout9-17_l dout18-26_l dout27-35_l dout18-26_r dout27-35_r b w 0 l b w 1 l b w 2 l b w 3 l i/o 0l - i/o 35l a 18l a 0l din_l addr_l oe l 5678 drw 01 be 3l be 2l be 1l be 0l r/ w l ce 0l ce 1l 512k x 36 memory array clk l abcd ft /pipe l 0/1 1d 0d 1c 0c 1b 0b 1a 0a b w 3 r , jtag tck trst tms tdo tdi 1 0 1/0 0d 1d 0c 1c 0b 1b 0a 1a abcd ft /pipe l 1/0 1/0 interrupt collision de te ction logic r/ w l ce 0 l ce1 l r/ w r ce 0 r ce1 r int l col l int r col r zz control logic zz l (1) zz r (1) a 18r features: true dual-port memory cells which allow simultaneous access of the same memory location high-speed data access ? commercial: 3.6ns (166mhz)/4.2ns (133mhz)(max.) ? industrial: 4.2ns (133mhz) (max.) selectable pipelined or flow-through output mode counter enable and repeat features dual chip enables allow for depth expansion without additional logic interrupt and collision detection flags full synchronous operation on both ports ? 6ns cycle time, 166mhz operation (12gbps bandwidth) ? fast 3.6ns clock to data out ? 1.5ns setup to clock and 0.5ns hold on all control, data, and address inputs @ 166mhz note: 1. the sleep mode pin shuts off all dynamic inputs, except jtag inputs, when asserted. all static inputs, i.e., pl/ ft x and optx and the sleep mode pins themselves (zzx) are not affected during sleep mode.
6.42 idt70t3539m high-speed 2.5v 512k x 36 dual-port synchronous static ram industrial and commercial temperature ranges 2 description: the idt70t3539m is a high-speed 512k x 36 bit synchronous dual- port ram. the memory array utilizes dual-port memory cells to allow simultaneous access of any address from both ports. registers on control, data, and address inputs provide minimal setup and hold times. the timing latitude provided by this approach allows systems to be designed with very short cycle times. with an input data register, the idt70t3539m has been optimized for applications having unidirectional or bidirectional data flow in bursts. an automatic power down feature, controlled by ce 0 and ce 1, permits the on-chip circuitry of each port to enter a very low standby power mode. the 70t3539m can support an operating voltage of either 3.3v or 2.5v on one or both ports, controllable by the opt pins. the power supply for the core of the device (v dd ) is at 2.5v.
6.42 idt70t3539m high-speed 2.5v 512k x 36 dual-port synchronous static ram industrial and commercial temperature ranges 3 pin configuration (1,2,3,4) notes: 1. all v dd pins must be connected to 2.5v power supply. 2. all v ddq pins must be connected to appropriate power supply: 3.3v if opt pin for that port is set to v dd (2.5v), and 2.5v if opt pin for that port is set to v ss (0v). 3. all v ss pins must be connected to ground supply. 4. package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch. 5. this package code is used to reference the package diagram. 6. this text does not indicate orientation of the actual part-marking. 70t3539m bc bc-256 (5) 256-pin bga top view (6) e16 i/o 14r d16 i/o 16r c16 i/o 16l b16 nc a16 nc a15 nc b15 i/o 17l c15 i/o 17r d15 i/o 15l e15 i/o 14l e14 i/o 13l d14 i/o 15r d13 v dd c12 a 6l c14 opt l b14 v dd a14 a 0l a12 a 5l b12 a 4l c11 ads l d12 v ddqr d11 v ddqr c10 clk l b1 1 repeat l a11 cnten l d8 v ddqr c8 be 1l a9 ce 1l d9 v ddql c9 be 0l b9 ce 0l d10 v ddql c7 a 7l b8 be 3l a8 be 2l b13 a 1l a13 a 2l a10 oe l d7 v ddqr b7 a 9l a7 a 8l b6 a 12l c6 a 10l d6 v ddql a5 a 14l b5 a 15l c5 a 13l d5 v ddql a4 b4 a 18l c4 d4 pipe/ ft l a3 nc b3 tdo c3 v ss d3 i/o 20l d2 i/o 19r c2 i/o 19l b2 nc a2 tdi a1 nc b1 i/o 18l c1 i/o 18r d1 i/o 20r e1 i/o 21r e2 i/o 21l e3 i/o 22l e4 v ddql f1 i/o 23l f2 i/o 22r f3 i/o 23r f4 v ddql g1 i/o 24r g2 i/o 24l g3 i/o 25l g4 v ddqr h1 i/o 26l h2 i/o 25r h3 i/o 26r h4 v ddqr j1 i/o 27l j2 i/o 28r j3 i/o 27r j4 v ddql k1 i/o 29r k2 i/o 29l k3 i/o 28l k4 v ddql l1 i/o 30l l2 i/o 31r l3 i/o 30r l4 v ddqr m1 i/o 32r m2 i/o 32l m3 i/o 31l m4 v ddqr n1 i/o 33l n2 i/o 34r n3 i/o 33r n4 p1 i/o 35r p2 i/o 34l p3 tms p4 r1 i/o 35l r2 nc r3 trst r4 a 18r t1 nc t2 tck t3 nc t4 p5 a 13r r5 a 15r p12 a 6r p8 be 1r p9 be 0r r8 be 3r t8 be 2r p10 clk r t11 cnten r p11 ads r r12 a 4r t12 a 5r p13 a 3r p7 a 7r r13 a 1r t13 a 2r r6 a 12r t5 a 14r t14 a 0r r14 opt r p14 i/o 0l p15 i/o 0r r15 nc t15 nc t16 nc r16 nc p16 i/o 1l n16 i/o 2r n15 i/o 1r n14 i/o 2l m16 i/o 4l m15 i/o 3l m14 i/o 3r l16 i/o 5r l15 i/o 4r l14 i/o 5l k16 i/o 7l k15 i/o 6l k14 i/o 6r j16 i/o 8l j15 i/o 7r j14 i/o 8r h16 i/o 10r h15 io 9l h14 i/o 9r g16 i/o 11r g15 i/o 11l g14 i/o 10l f16 i/o 12l f14 i/o 12r f15 i/o 13r r9 ce 0r r11 repeat r t6 a 11r t9 ce 1r a6 a 11l b10 r/ w l c13 a 3l p6 a 10r r10 r/ w r r7 a 9r t10 oe r t7 a 8r , e5 v dd e6 v dd e7 int l e8 v ss e9 v ss e10 v ss e11 v dd e12 v dd e13 v ddqr f5 v dd f6 nc f8 v ss f9 v ss f10 v ss f12 v dd f13 v ddqr g5 v ss g6 v ss g7 v ss g8 v ss g9 v ss g10 v ss g11 v ss g12 v ss g13 v ddql h5 v ss h6 v ss h7 v ss h8 v ss h9 v ss h10 v ss h11 v ss h12 v ss h13 v ddql j5 zz r j6 v ss j7 v ss j8 v ss j9 v ss j10 v ss j11 v ss j12 zz l j13 v ddqr k5 v ss k6 v ss k7 v ss k8 v ss l5 v dd l6 nc l7 col r l8 v ss m5 v dd m6 v dd m7 int r m8 v ss n5 v ddqr n6 v ddqr n7 v ddql n8 v ddql k9 v ss k10 v ss k11 v ss k12 v ss l9 v ss l10 v ss l11 v ss l12 v dd m9 v ss m10 v ss m11 v dd m12 v dd n9 v ddqr n10 v ddqr n11 v ddql n12 v ddql k13 v ddqr l13 v ddql m13 v ddql n13 v dd f7 col l f11 v ss 5678 drw 02d , 1 0 / 0 7 / 0 3 a 17r a 17l a 16l a 16r pipe/ ft r
6.42 idt70t3539m high-speed 2.5v 512k x 36 dual-port synchronous static ram industrial and commercial temperature ranges 4 pin names left port right port names ce 0l , ce 1l ce 0r , ce 1r chip enables (input) (5) r/ w l r/ w r read/write enable (input) oe l oe r output enable (input) a 0l - a 18l a 0r - a 18r address (input) i/o 0l - i/o 35l i/o 0r - i/o 35r data input/output clk l clk r clock (input) pl/ ft l pl/ ft r pipeline/flow-through (input) ads l ads r address strobe enable (input) cnten l cnten r counter enable (input) repeat l repeat r counter repeat (3) be 0l - be 3l be 0r - be 3r byte enables (9-bit bytes) (input) (5) v ddql v ddqr power (i/o bus) (3.3v or 2.5v) (1) (input ) opt l opt r option for selecting v ddqx (1,2) (input) zz l zz r sleep mode pin (4) (input) v dd power (2.5v) (1) (input) v ss ground (0v) (input) tdi test data input tdo test data output tck test logic clock (10mhz) (input) tms test mode select (input) trst reset (initialize tap controller) (input) int l int r interrupt flag (output) col l col r collision alert (output) 5678 tbl 01 notes: 1. v dd , opt x , and v ddqx must be set to appropriate operating levels prior to applying inputs on the i/os and controls for that port. 2. opt x selects the operating voltage levels for the i/os and controls on that port. if opt x is set to v dd (2.5v), then that port's i/os and controls will operate at 3.3v levels and v ddqx must be supplied at 3.3v. if opt x is set to v ss (0v), then that port's i/os and address controls will operate at 2.5v levels and v ddqx must be supplied at 2.5v. the opt pins are independent of one another?both ports can operate at 3.3v levels, both can operate at 2.5v levels, or either can operate at 3.3v with the other at 2.5v. 3. when repeat x is asserted, the counter will reset to the last valid address loaded via ads x . 4. the sleep mode pin shuts off all dynamic inputs, except jtag inputs, when asserted. all static inputs, i.e., pl/ ft x and optx and the sleep mode pins themselves (zzx) are not affected during sleep mode. it is recommended that boundry scan not be operated during sleep mode. 5. chip enables and byte enables are double buffered when pl/ ft = v ih , i.e., the signals take two cycles to deselect.
6.42 idt70t3539m high-speed 2.5v 512k x 36 dual-port synchronous static ram industrial and commercial temperature ranges 5 notes: 1. "h" = v ih, "l" = v il, "x" = don't care. 2. ads , cnten , repeat = v ih . 3. oe and zz are asynchronous input signals. 4. it is possible to read or write any combination of bytes during a given access. a few representative samples have been illust rated here. truth table i?read/write and enable control (1,2,3,4) oe clk ce 0 ce 1 be 3 be 2 be 1 be 0 r/ w zz byte 3 i/o 27-35 byte 2 i/o 18-26 byte 1 i/o 9-17 byte 0 i/o 0-8 mode x hxxxxxx lhigh-zhigh-zhigh-zhigh-zdeselected?power down x xlxxxxx lhigh-zhigh-zhigh-zhigh-zdeselected?power down x l hhhhhx l high-zhigh-zhigh-zhigh-zall bytes deselected x l hhhhl l l high-zhigh-zhigh-z d in write to byte 0 only x l h h h l h l l high-z high-z d in high-z write to byte 1 only x lhhlhhllhigh-z d in high-z high-z write to byte 2 only x lhlhhhll d in high-z high-z high-z write to byte 3 only x l h h h l l l l high-z high-z d in d in write to lower 2 bytes only x lhllhhll d in d in high-z high-z write to upper 2 bytes only x lhllllll d in d in d in d in write to all bytes l l hhhhl h l high-zhigh-zhigh-z d out re ad byte 0 only l l h h h l h h l high-z high-z d out high-z re ad byte 1 only l lhhlhhhlhigh-z d out high-z high-z read byte 2 only l lhlhhhhl d out high-z high-z high-z read byte 3 only l l h h h l l h l high-z high-z d out d out read lower 2 bytes only l lhllhhhl d out d out hig h-z high-z re ad up pe r 2 byte s only l lhllllhl d out d out d out d out re ad all bytes h xxxxxxx lhigh-zhigh-zhigh-zhigh-zoutputs disabled xxxxxxxxx hhigh-zhigh-zhigh-zhigh-zsleep mode 5678 tbl 02 truth table ii?address counter control (1,2) notes: 1. "h" = v ih, "l" = v il, "x" = don't care. 2. read and write operations are controlled by the appropriate setting of r/ w , ce 0 , ce 1 , be n and oe . 3. outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle. 4. ads and repeat are independent of all other memory control signals including ce 0 , ce 1 and be n 5. the address counter advances if cnten = v il on the rising edge of clk, regardless of all other memory control signals including ce 0 , ce 1 , be n. 6. when repeat is asserted, the counter will reset to the last valid address loaded via ads . this value is not set at power-up: a known location should be loaded via ads during initialization if desired. any subsequent ads access during operations will update the repeat address location. address previous internal address internal address used clk ads cnten repeat (6) i/o (3) mode an x an l (4) xhd i/o (n) external address used xanan + 1 h l (5) hd i/o (n+1) counter enabled?internal address generation xan + 1an + 1 hh hd i/o (n+1) external address blocked?counter disabled (an + 1 reused) xxan xx l (4) d i/o (n) counter set to last valid ads load 5678 tbl 03
6.42 idt70t3539m high-speed 2.5v 512k x 36 dual-port synchronous static ram industrial and commercial temperature ranges 6 recommended operating temperature and supply voltage (1) notes: 1. this is the parameter ta. this is the "instant on" case temperature. grade ambient temperature gnd v dd commercial 0 o c to +70 o c0v2.5v + 100mv industrial -40 o c to +85 o c0v2.5v + 100mv 5678 tbl 04 recommended dc operating conditions with v ddq at 3.3v notes: 1. v il (min.) = -1.0v for pulse width less than t cyc /2, or 5ns, whichever is less. 2. v ih (max.) = v ddq + 1.0v for pulse width less than t cyc /2 or 5ns, whichever is less. 3. to select operation at 3.3v levels on the i/os and controls of a given port, the opt pin for that port must be set to v dd (2.5v), and v ddqx for that port must be supplied as indicated above. symbol parameter min. typ. max. unit v dd core supply voltage 2.4 2.5 2.6 v v ddq i/o supply voltage (3) 3.15 3.3 3.45 v v ss ground 0 0 0 v v ih input high voltage (address, control &data i/o inputs) (3) 2.0 ____ v ddq + 150mv (2) v v ih input high voltage _ jtag 1.7 ____ v dd + 100mv (2) v v ih input high voltage - zz, opt, pipe/ ft v dd - 0.2v ____ v dd + 100mv (2) v v il input low voltage -0.3 (1) ____ 0.8 v v il input low voltage - zz, opt, pipe/ ft -0.3 (1) ____ 0.2 v 5678 tbl 05b recommended dc operating conditions with v ddq at 2.5v notes: 1. v il (min.) = -1.0v for pulse width less than t cyc /2 or 5ns, whichever is less. 2. v ih (max.) = v ddq + 1.0v for pulse width less than t cyc /2 or 5ns, whichever is less. 3. to select operation at 2.5v levels on the i/os and controls of a given port, the opt pin for that port must be set to v ss (0v), and v ddqx for that port must be supplied as indicated above. symbol parameter min. typ. max. unit v dd core supply voltage 2.4 2.5 2.6 v v ddq i/o supply voltage (3) 2.4 2.5 2.6 v v ss ground 0 0 0 v v ih input high volltage (address, control & data i/o inputs) (3) 1.7 ____ v ddq + 100mv (2) v v ih input high voltage _ jtag 1.7 ____ v dd + 100mv (2) v v ih input high voltage - zz, opt, pipe/ ft v dd - 0.2v ____ v dd + 100mv (2) v v il input low voltage -0.3 (1) ____ 0.7 v v il input low voltage - zz, opt, pipe/ ft -0.3 (1) ____ 0.2 v 5678 tbl 05a
6.42 idt70t3539m high-speed 2.5v 512k x 36 dual-port synchronous static ram industrial and commercial temperature ranges 7 absolute maximum ratings (1) symbol rating commercial & industrial unit v term (v dd ) v dd terminal voltage with respect to gnd -0.5 to 3.6 v v term (2) (v ddq ) v ddq terminal voltage with respect to gnd -0.3 to v ddq + 0.3 v v term (2) (inputs and i/o's) input and i/o terminal voltag e with respect to gnd -0.3 to v ddq + 0.3 v t bias (3) temperature under bias -55 to +125 o c t stg storage temperature -65 to +150 o c t jn junction temperature +150 o c i out (for v ddq = 3.3v) dc output current 50 ma i out (for v ddq = 2.5v) dc output current 40 ma 5678 tbl 06 notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. this is a steady-state dc parameter that applies after the power supply has reached its nominal operating value. power sequencing is not necessary; however, the voltage on any input or i/o pin cannot exceed v ddq during power supply ramp up. 3. ambient temperature under dc bias. no ac conditions. chip deselected. notes: 1. these parameters are determined by device characterization, but are not production tested. 2. 3dv references the interpolated capacitance when the input and output switch from 0v to 3v or from 3v to 0v. 3. c out also references c i/o . capacitance (1) (t a = +25c, f = 1.0mh z ) pqfp only symbol parameter conditions (2) max. unit c in input capacitance v in = 3dv 15 pf c out (3) output capacitance v out = 3dv 10.5 pf 5678 tbl 07 dc electrical characteristics over the operating temperature and supply voltage range (v dd = 2.5v 100mv) symbol parameter test conditions 70t3539ms unit min. max. |i li | input leakage current (1) v ddq = max., v in = 0v to v ddq ___ 10 a |i li | jtag & zz input leakage current (1,2) v dd = max. , v in = 0v to v dd ___ 30 a |i lo | output leakage current (1,3) ce 0 = v ih or ce 1 = v il , v out = 0v to v ddq ___ 10 a v ol (3.3v) output low voltage (1) i ol = +4ma, v ddq = min. ___ 0.4 v v oh (3.3v) output high voltage (1) i oh = -4ma, v ddq = min. 2.4 ___ v v ol (2.5v) output low voltage (1) i ol = +2ma, v ddq = min. ___ 0.4 v v oh (2.5v) output high voltage (1) i oh = -2ma, v ddq = min. 2.0 ___ v 5678 tbl 08 notes: 1. v ddq is selectable (3.3v/2.5v) via opt pins. refer to p.5 for details. 2. applicable only for tms, tdi and trst inputs. 3. outputs tested in tri-state mode.
6.42 idt70t3539m high-speed 2.5v 512k x 36 dual-port synchronous static ram industrial and commercial temperature ranges 8 dc electrical characteristics over the operating temperature and supply voltage range (3) (v dd = 2.5v 100mv) notes: 1. at f = f max , address and control lines (except output enable) are cycling at the maximum frequency clock cycle of 1/t cyc , using "ac test conditions". 2. f = 0 means no address, clock, or control lines change. applies only to input at cmos level standby. 3. port "a" may be either left or right port. port "b" is the opposite from port "a". 4. v dd = 2.5v, t a = 25c for typ, and are not production tested. i dd dc (f=0) = 30ma (typ). 5. ce x = v il means ce 0x = v il and ce 1x = v ih ce x = v ih means ce 0x = v ih or ce 1x = v il ce x < 0.2v means ce 0x < 0.2v and ce 1x > v ddq - 0.2v ce x > v ddq - 0.2v means ce 0x > v ddq - 0.2v or ce 1x - 0.2v "x" represents "l" for left port or "r" for right port. 6. i sb 1 , i sb 2 and i sb 4 will all reach full standby levels ( i sb 3) on the appropriate port(s) if zz l and/or zz r = v ih . 70t3539ms166 com'l only 70t3539ms133 com'l & ind symbol parameter test condition version typ. (4) max. typ. (4) max. unit i dd dynamic operating current (both ports active) ce l and ce r = v il , outputs disabled, f = f max (1) com'l s 640 900 520 740 ma ind s ___ ___ 520 900 i sb1 (6) standby current (both ports - ttl le ve l inputs ) ce l = ce r = v ih f = f max (1) com'l s 350 460 280 380 ma ind s ___ ___ 280 470 i sb2 (6) standby current (one port - ttl le ve l inputs ) ce "a" = v il and ce "b" = v ih (5) active port outputs disabled, f=f max (1) com'l s 500 650 400 500 ma ind s ___ ___ 400 620 i sb3 full standby current (both ports - cmos le ve l inputs ) both ports ce l and ce r > v ddq - 0.2v, v in > v ddq - 0.2v or v in < 0.2v, f = 0 (2) com'l s 12 20 12 20 ma ind s ___ ___ 12 25 i sb4 (6) full standby current (one port - cmos le ve l inputs ) ce "a" < 0.2v and ce "b" > v ddq - 0.2v (5) v in > v ddq - 0.2v or v in < 0.2v active port, outputs disabled, f = f max (1) com'l s 500 650 400 500 ma ind s ___ ___ 400 620 izz sleep mode current (both ports - ttl le ve l inputs ) zz l = zz r = v ih f=f max (1) com'l s 12 20 12 20 ma ind s ___ ___ 12 25 5678 tbl 09
6.42 idt70t3539m high-speed 2.5v 512k x 36 dual-port synchronous static ram industrial and commercial temperature ranges 9 ac test conditions (v ddq - 3.3v/2.5v) figure 1. ac output test load. input pulse levels (address & controls) input pulse le ve ls (i/os) input ris e/fall times input timing reference levels output reference levels output load gnd to 3 . 0v/gnd to 2.4v gnd to 3.0v/gnd to 2.4v 2ns 1.5v/1.25v 1.5v/1.25v figure 1 5678 tbl 10 1.5v/1.25 50 ? 50 ? 5678 drw 03 10pf (tester) d ata out , ? capacitance (pf) from ac test load 5678 drw 04 ? tcd ( typical, ns)
6.42 idt70t3539m high-speed 2.5v 512k x 36 dual-port synchronous static ram industrial and commercial temperature ranges 10 ac electrical characteristics over the operating temperature range (read and write cycle timing) (2,3) (v dd = 2.5v 100mv, t a = 0c to +70c) notes: 1. the pipelined output parameters (t cyc2 , t cd2 ) apply to either or both left and right ports when ft /pipe x = v dd (2.5v). flow-through parameters (t cyc1 , t cd1 ) apply when ft /pipe = v ss (0v) for that port. 2. all input signals are synchronous with respect to the clock except for the asynchronous output enable ( oe ), ft /pipe and opt. ft /pipe and opt should be treated as dc signals, i.e. steady state during operation. 3. these values are valid for either level of v ddq (3.3v/2.5v). see page 6 for details on selecting the desired operating voltage levels for each port. 4. guaranteed by design (not production tested). 70t3539ms166 com'l only 70t3539ms133 com'l & ind symbol parameter min. max. min. max. unit t cyc1 clock cycle time (flow-through) (1) 20 ____ 25 ____ ns t cyc2 clock cycle time (pipelined) (1) 6 ____ 7.5 ____ ns t ch1 clock high time (flow-through) (1) 8 ____ 10 ____ ns t cl1 clock low time (flo w-through) (1) 8 ____ 10 ____ ns t ch2 clock high time (pipelined) (2) 2.4 ____ 3 ____ ns t cl2 clock low time (pipelined) (1) 2.4 ____ 3 ____ ns t sa address setup time 1.7 ____ 1.8 ____ ns t ha address hold time 0.5 ____ 0.5 ____ ns t sc chip enable setup time 1.7 ____ 1.8 ____ ns t hc chip enable hold time 0.5 ____ 0.5 ____ ns t sb byte enable setup time 1.7 ____ 1.8 ____ ns t hb byte enable hold time 0.5 ____ 0.5 ____ ns t sw r/w setup time 1.7 ____ 1.8 ____ ns t hw r/w hold time 0.5 ____ 0.5 ____ ns t sd input data setup time 1.7 ____ 1.8 ____ ns t hd input data hold time 0.5 ____ 0.5 ____ ns t sad ads setup time 1.7 ____ 1.8 ____ ns t had ads ho ld time 0.5 ____ 0.5 ____ ns t scn cnten setup time 1.7 ____ 1.8 ____ ns t hcn cnten ho ld time 0.5 ____ 0.5 ____ ns t srpt repeat setup time 1.7 ____ 1.8 ____ ns t hrpt repeat ho ld time 0.5 ____ 0.5 ____ ns t oe output enab le to data valid ____ 4.4 ____ 4.6 ns t olz (6) output enab le to output low-z 1 ____ 1 ____ ns t ohz (6) output enable to output high-z 1 3.6 1 4.2 ns t cd1 clock to data valid (flow-through) (1) ____ 12 ____ 15 ns t cd2 clock to data valid (pipelined) (1) ____ 3.6 ____ 4.2 ns t dc data output hold after clo ck hig h 1 ____ 1 ____ ns t ckhz (6) clock high to output high-z 1 3.6 1 4.2 ns t cklz (6) clock high to output low-z 1 ____ 1 ____ ns t ins interrupt flag set time ____ 7 ____ 7ns t inr interrupt flag rese t time ____ 7 ____ 7ns t cols collision flag set time ____ 3.6 ____ 4.2 ns t colr collision flag reset time ____ 3.6 ____ 4.2 ns t zzs c sleep mode set cycles 2 ____ 2 ____ cycles t zzrc sleep mode recovery cycles 3 ____ 3 ____ cycles port-to-port delay t co clock-to-clock offset 5 ____ 6 ____ ns t ofs clock-to-clock offset for collision detection please refer to collision detection timing table on page 19 5678 tbl 11
6.42 idt70t3539m high-speed 2.5v 512k x 36 dual-port synchronous static ram industrial and commercial temperature ranges 11 an an + 1 an + 2 an + 3 t cyc2 t ch2 t cl2 r/ w address ce 0 clk ce 1 be n (3) data out oe t cd2 t cklz qn qn + 1 qn + 2 t ohz t olz t oe 5678 drw 05 (1) (1) t sc t hc t sb t hb t sw t hw t sa t ha t dc t sc t hc t sb t hb (4) (1 latency) (5) (5) , timing waveform of read cycle for pipelined operation ( ft /pipe 'x' = v ih ) (1,2) notes: 1. oe is asynchronously controlled; all other inputs depicted in the above waveforms are synchronous to the rising clock edge. 2. ads = v il , cnten and repeat = v ih . 3. the output is disabled (high-impedance state) by ce 0 = v ih , ce 1 = v il , be n = v ih following the next rising edge of the clock. refer to truth table 1. 4. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 5. if be n was high, then the appropriate byte of data out for qn + 2 would be disabled (high-impedance state). 6. "x" denotes left or right port. the diagram is with respect to that port. timing waveform of read cycle for flow-through output ( ft /pipe "x" = v il ) (1,2,6) an an + 1 an + 2 an + 3 t cyc1 t ch1 t cl1 r/ w address data out ce 0 clk oe t sc t hc t cd1 t cklz qn qn + 1 qn + 2 t ohz t olz t oe t ckhz 5678 drw 06 (5) (1) ce 1 be n (3) t sb t hb t sw t hw t sa t ha t dc t dc (4) t sc t hc t sb t hb ,
6.42 idt70t3539m high-speed 2.5v 512k x 36 dual-port synchronous static ram industrial and commercial temperature ranges 12 , t sc t hc ce 0(b1) a ddress (b1) a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha clk q 0 q 1 q 3 data out(b1) t ch2 t cl2 t cyc2 a ddress (b2) a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha ce 0(b2) data out(b2) q 2 q 4 t cd2 t cd2 t ckhz t cd2 t cklz t dc t ckhz t cd2 t cklz t sc t hc t ckhz t cklz t cd2 a 6 a 6 t dc t sc t hc t sc t hc 5678 drw 07 timing waveform of a multi-device pipelined read (1,2) notes: 1. b1 represents device #1; b2 represents device #2. each device consists of one idt70t3539m for this waveform, and are setup for depth expansion in this example. address (b1) = address (b2) in this situation. 2. be n , oe , and ads = v il ; ce 1(b1) , ce 1(b2) , r/ w , cnten , and repeat = v ih . timing waveform of a multi-device flow-through read (1,2) t sc t hc ce 0(b1) address (b1) a 0 a 1 a 2 a 3 a 4 a 5 t sa t h a clk 5678 drw 08 d 0 d 3 t cd1 t cklz t ckhz (1) (1) d 1 data out(b1) t ch1 t cl1 t cyc1 (1) address (b2) a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha ce 0(b2) data out(b2) d 2 d 4 t cd1 t cd1 t ckhz t dc t cd1 t cklz t sc t hc (1) t ckhz (1) t cklz (1) t cd1 a 6 a 6 t dc t sc t hc t sc t hc d 5 t cd1 t cklz (1) t ckhz (1) ,
6.42 idt70t3539m high-speed 2.5v 512k x 36 dual-port synchronous static ram industrial and commercial temperature ranges 13 clk "a" r/ w "a " address "a" data in"a" clk "b" r/ w "b" address "b" data out"b" t sw t hw t sa t ha t sd t hd t sw t hw t sa t ha t co (3 ) t cd2 no match valid no match match match valid 5678 drw 09 t dc , timing waveform of left port write to pipelined right port read (1,2,4) notes: 1. ce 0 , be n , and ads = v il ; ce 1 , cnten , and repeat = v ih . 2. oe = v il for port "b", which is being read from. oe = v ih for port "a", which is being written to. 3. if t co < minimum specified, then data from port "b" read is not valid until following port "b" clock cycle (ie, time from write to val id read on opposite port will be t co + 2 t cyc2 + t cd2 ). if t co > minimum, then data from port "b" read is available on first port "b" clock cycle (ie, time from write to valid read on oppos ite port will be t co + t cyc2 + t cd2 ). 4. all timing is the same for left and right ports. port "a" may be either left or right port. port "b" is the opposite of port "a" timing waveform with port-to-port flow-through read (1,2,4) data in "a" clk "b" r/ w "b" address "a" r/ w "a" clk "a" address "b" no match match no match match valid t cd1 t dc data out "b" 5678 drw 10 valid valid t sw t hw t sa t ha t sd t hd t hw t cd1 t co t dc t sa t sw t ha (3) , notes: 1. ce 0 , be n, and ads = v il ; ce 1 , cnten , and repeat = v ih . 2. oe = v il for the right port, which is being read from. oe = v ih for the left port, which is being written to. 3. if t co < minimum specified, then data from port "b" read is not valid until following port "b" clock cycle (i.e., time from write to v alid read on opposite port will be t co + t cyc + t cd1 ). if t co > minimum, then data from port "b" read is available on first port "b" clock cycle (i.e., time from write to valid read on oppo site port will be t co + t cd1 ). 4. all timing is the same for both left and right ports. port "a" may be either left or right port. port "b" is the opposite of port "a".
6.42 idt70t3539m high-speed 2.5v 512k x 36 dual-port synchronous static ram industrial and commercial temperature ranges 14 r/ w address an an +1 an + 2 an + 2 an + 3 an + 4 data in dn + 2 ce 0 clk 5678 drw 11 qn qn + 3 data out ce 1 be n t cd2 t ckhz t cklz t cd2 t sc t hc t sb t hb t sw t hw t sa t ha t ch2 t cl2 t cyc2 read nop read t sd t hd (3) (1) t sw t hw write (4) , timing waveform of pipelined read-to-write-to-read ( oe = v il ) (2) notes: 1. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 2. ce 0 , be n , and ads = v il ; ce 1 , cnten , and repeat = v ih . "nop" is "no operation". 3. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 4. "nop" is "no operation." data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. r/ w address an an +1 an + 2 an + 3 an + 4 an + 5 data in dn + 3 dn + 2 ce 0 clk 5678 drw 12 data out qn qn + 4 ce 1 be n oe t ch2 t cl2 t cyc2 t cklz t cd2 t ohz t cd2 t sd t hd read write read t sc t hc t sb t hb t sw t hw t sa t ha (3) (1) t sw t hw (4) , timing waveform of pipelined read-to-write-to-read ( oe controlled) (2) notes: 1. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 2. ce 0 , be n , and ads = v il ; ce 1 , cnten , and repeat = v ih . 3. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 4. this timing does not meet requirements for fastest speed grade. this waveform indicates how logically it could be done if tim ing so allows.
6.42 idt70t3539m high-speed 2.5v 512k x 36 dual-port synchronous static ram industrial and commercial temperature ranges 15 timing waveform of flow-through read-to-write-to-read ( oe = v il ) (2) timing waveform of flow-through read-to-write-to-read ( oe controlled) (2) notes: 1. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 2. ce 0 , be n, and ads = v il ; ce 1 , cnten , and repeat = v ih . 3. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 4. "nop" is "no operation." data in memory at the selected address may be corrupted and should be re-written to guarantee data i ntegrity. r/ w address an an +1 an + 2 an + 2 an + 3 an + 4 data in dn + 2 ce 0 clk 5678 drw 13 qn data out ce 1 be n t cd1 qn + 1 t ch1 t cl1 t cyc1 t sd t hd t cd1 t cd1 t dc t ckhz qn + 3 t cd1 t dc t sc t hc t sb t hb t sw t hw t sa t ha read nop read t cklz (3) (1) t sw t hw write (5) , r/ w address an an +1 an + 2 an + 3 an + 4 an + 5 (3) data in dn + 2 ce 0 clk 5678 drw 14 qn data out ce 1 be n t cd1 t ch1 t cl1 t cyc1 t sd t hd t cd1 t dc qn + 4 t cd1 t dc t sc t hc t sb t hb t sw t hw t sa t ha read write read t cklz (1) dn + 3 t ohz t sw t hw oe t oe ,
6.42 idt70t3539m high-speed 2.5v 512k x 36 dual-port synchronous static ram industrial and commercial temperature ranges 16 address an clk data out qx - 1 (2) qx qn qn + 2 (2) qn + 3 ads cnten t cyc2 t ch2 t cl2 5678 drw 15 t sa t ha t sad t had t cd2 t dc read external address read with counter counter hold t sad t had t scn t hcn read with counter qn + 1 , timing waveform of pipelined read with address counter advance (1) notes: 1. ce 0 , oe , be n = v il ; ce 1 , r/ w , and repeat = v ih . 2. if there is no address change via ads = v il (loading a new address) or cnten = v il (advancing the address), i.e. ads = v ih and cnten = v ih , then the data output remains constant for subsequent clocks. timing waveform of flow-through read with address counter advance (1) address an clk data out qx (2) qn qn + 1 qn + 2 qn + 3 (2) qn + 4 ads cnten t cyc1 t ch1 t cl1 5678 drw 16 t sa t ha t sad t had read external address read with counter counter hold t cd1 t dc t sad t had t scn t hcn read with counter ,
6.42 idt70t3539m high-speed 2.5v 512k x 36 dual-port synchronous static ram industrial and commercial temperature ranges 17 address an t cyc2 clk data in r/ w repeat 5678 drw 18 internal (3) address ads cnten write to ads address an advance counter write to an+1 advance counter write to an+2 hold counter write to an+2 repeat read last ads address an data out t sa t ha , an , t sad t had t sw t hw t scn t hcn t srpt t hrpt t sd t hd t cd1 an+1 an+2 an+2 an an+1 an+2 an+2 d 0 d 1 d 2 d 3 an an+1 an+2 an+2 advance counter read an+1 advance counter read an+2 hold counter read an+2 (4) timing waveform of write with address counter advance (flow-through or pipelined inputs) (1) timing waveform of counter repeat (2,6) address an clk data in dn dn + 1 dn + 1 dn + 2 ads cnten t ch2 t cl2 t cyc2 5678 drw 17 internal (3) address an (7) an + 1 an + 2 an + 3 an + 4 dn + 3 dn + 4 t sa t ha t sad t had write counter hold write with counter write external address write with counter t sd t hd t scn t hc n , notes: 1. ce 0 , be n , and r/ w = v il ; ce 1 and repeat = v ih . 2. ce 0 , be n = v il ; ce 1 = v ih . 3. the "internal address" is equal to the "external address" when ads = v il and equals the counter output when ads = v ih . 4. no dead cycle exists during repeat operation. a read or write cycle may be coincidental with the counter repeat cycle: address loaded by last valid ads load will be accessed. for more information on repeat function refer to truth table ii. 5. cnten = v il advances internal address from ?an? to ?an +1?. the transition shown indicates the time required for the counter to advance. t he ?an +1?address is written to during this cycle. 6. for pipelined mode user should add 1 cycle latency for outputs as per timing waveform of read cycle for pipelined operations.
6.42 idt70t3539m high-speed 2.5v 512k x 36 dual-port synchronous static ram industrial and commercial temperature ranges 18 truth table iii ? interrupt flag (1) left port right port function clk l r/ w l (2) ce l (2) a 18l -a 0l int l clk r r/ w r (2) ce r (2) a 18r -a 0r int r l l 7ffff x x x x l set right int r flag xx x x h l 7ffff h reset right int r flag xx x l l l 7fffe x set left int l flag h l 7fffe h x x x x reset left int l flag 5678 tbl 12 notes: 1. int l and int r must be initialized at power-up by resetting the flags. 2. ce 0 = v il and ce 1 = v ih . r/ w and ce are synchronous with respect to the clock and need valid set-up and hold times. 3. address is for internal register, not the external bus, i.e., address needs to be qualified by one of the address counter con trol signals. waveform of interrupt timing (2) notes: 1. ce 0 = v il and ce 1 = v ih 2. all timing is the same for left and right ports. 3. address is for internal register, not the external bus, i.e., address needs to be qualified by one of the address counter con trol signals. t sw t hw 7ffff clk r ce r (1) a ddress r (3) t sa t ha 7ffff t sc t hc t inr clk l r/ w l address l (3) ce l (1) t sa t ha t sc t hc 5678 drw 19 int r t ins r/ w r t sw t hw
6.42 idt70t3539m high-speed 2.5v 512k x 36 dual-port synchronous static ram industrial and commercial temperature ranges 19 t sa t ha (3) t cols t colr a 3 ha t sa t t cols t colr 5678 drw 20 col r col l (4) clk r a ddress r a 0 a 1 a 2 t ofs (4) clk l address l a 0 a 1 a 2 a 3 t ofs waveform of collision timing (1,2) left port right port function clk l r/ w l (1) ce l (1) a 18l -a 0l (2) col l clk r r/ w r (1) ce r (1) a 18r -a 0r (2) col r hlmatchh hlmatchh both ports reading. not a valid collision. no flag output on either port. hlmatchl llmatchh left port reading, right port writing. valid collision, flag output on left port. llmatchh hlmatchl right port reading, left port writing. valid collision, flag output on right port. llmatchl llmatchl both ports writing. valid collision. flag output on both ports. 5678 tbl 14 truth table iv ? collision detection flag notes: 1. ce 0 = v il and ce 1 = v ih . r/ w and ce are synchronous with respect to the clock and need valid set-up and hold times. 2. address is for internal register, not the external bus, i.e., address needs to be qualified by one of the address counter con trol signals. cycle time t ofs (ns) region 1 (ns) (1) region 2 (ns) (2) 5ns 0 - 2.8 2.81 - 4.6 6ns 0 - 3.8 3.81 - 5.6 7.5ns 0 - 5.3 5.31 - 7.1 5678 tbl 13 collision detection timing (3,4) notes: 1. region 1 both ports show collision after 2nd cycle for addresses 0, 2, 4 etc. 2. region 2 leading port shows collision after 3rd cycle for addresses 0, 3, 6, etc. while trailing port shows collision after 2nd cycle for addresses 0, 2, 4 etc. 3. all the production units are tested to midpoint of each region. 4. these ranges are based on characterization of a typical device. notes: 1. ce 0 = v il , ce 1 = v ih . 2. for reading port, oe is a don't care on the collision detection logic. please refer to truth table iv for specific cases. 3. leading port output flag might output 3t cyc 2 + t cols after address match. 4. address is for internal register, not the external bus, i.e., address needs to be qualified by one of the address counter con trol signals.
6.42 idt70t3539m high-speed 2.5v 512k x 36 dual-port synchronous static ram industrial and commercial temperature ranges 20 timing waveform - entering sleep mode (1,2) timing waveform - exiting sleep mode (1,2) notes: 1. ce 1 = v ih. 2. all timing is same for left and right ports. 3. ce 0 has to be deactivated ( ce 0 = v ih ) three cycles prior to asserting zz (zzx = v ih ) and held for two cycles after asserting zz (zzx = v ih ). 4. ce 0 has to be deactivated ( ce 0 = v ih ) one cycle prior to de-asserting zz (zzx = v il ) and held for three cycles after de-asserting zz (zzx = v il ). 5. the device must be in read mode (r/ w high) when exiting sleep mode. outputs are active but data is not valid until the following cycle. (3) r/ w data out r/ w oe (4) dn dn+1 an+1 an (5) (5)
6.42 idt70t3539m high-speed 2.5v 512k x 36 dual-port synchronous static ram industrial and commercial temperature ranges 21 functional description the idt70t3539m provides a true synchronous dual-port static ram interface. registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. all internal registers are clocked on the rising edge of the clock signal, however, the self-timed internal write pulse width is independent of the cycle time. an asynchronous output enable is provided to ease asyn- chronous bus interfacing. counter enable inputs are also provided to stall the operation of the address counters for fast interleaved memory applications. a high on ce 0 or a low on ce 1 for one clock cycle will power down the internal circuitry to reduce static power consumption. multiple chip enables allow easier banking of multiple idt70t3539ms for depth expansion configurations. two cycles are required with ce 0 low and ce 1 high to re-activate the outputs. interrupts if the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. the left port interrupt flag ( int l ) is asserted when the right port writes to memory location 7fffe (hex), where a write is defined as ce r = r/ w r = v il per the truth table. the left port clears the interrupt through access of address location 7fffe when ce l = v il and r/ w l = v ih . likewise, the right port interrupt flag ( int r ) is asserted when the left port writes to memory location 7ffff (hex) and to clear the interrupt flag ( int r ), the right port must read the memory location 7ffff. the message (36 bits) at 7fffe or 7ffff is user-defined since it is an addressable sram location. if the interrupt function is not used, address locations 7fffe and 7ffff are not used as mail boxes, but as part of the random access memory. refer to truth table iii for the interrupt operation. collision detection sleep mode tthe idt70t3539m is equipped with an optional sleep or low power mode on both ports. the sleep mode pin on both ports is asynchronous and active high. during normal operation, the zz pin is pulled low. when zz is pulled high, the port will enter sleep mode where it will meet lowest possible power conditions. the sleep mode timing diagram shows the modes of operation: normal operation, no read/write allowed and sleep mode. for normal operation all inputs must meet setup and hold times prior to sleep and after recovering from sleep. clocks must also meet cycle high and low times during these periods. three cycles prior to asserting zz (zzx = v ih ) and three cycles after de-asserting zz (zzx = v il ), the device must be disabled via the chip enable pins. if a write or read operation occurs during these periods, the memory array may be corrupted. validity of data out from the ram cannot be guaranteed immediately after zz is asserted (prior to being in sleep). when exiting sleep mode, the device must be in read mode (r/ w x = v ih )when chip enable is asserted, and the chip enable must be valid for one full cycle before a read will result in the output of valid data. during sleep mode the ram automatically deselects itself. the ram disconnects its internal clock buffer. the external clock may continue to run without impacting the rams sleep current (i zz ). all outputs will remain in high-z state while in sleep mode. all inputs are allowed to toggle. the ram will not be selected and will not perform any reads or writes. collision is defined as an overlap in access between the two ports resulting in the potential for either reading or writing incorrect data to a specific address. for the specific cases: (a) both ports reading - no data is corrupted, lost, or incorrectly output, so no collision flag is output on either port. (b) one port writing, the other port reading - the end result of the write will still be valid. however, the reading port might capture data that is in a state of transition and hence the reading port?s collision flag is output. (c) both ports writing - there is a risk that the two ports will interfere with each other, and the data stored in memory will not be a valid write from either port (it may essentially be a random combination of the two). therefore, the collision flag is output on both ports. please refer to truth table iv for all of the above cases. the alert flag ( col x ) is asserted on the 2nd or 3rd rising clock edge of the affected port following the collision, and remains low for one cycle. please refer to collision detection timing table on page 19. during that next cycle, the internal arbitration is engaged in resetting the alert flag (this avoids a specific requirement on the part of the user to reset the alert flag). if two collisions occur on subsequent clock cycles, the second collision may not generate the appropriate alert flag. a third collision will generate the alert flag as appropriate. in the event that a user initiates a burst access on both ports with the collision detection on the idt70t3539m represents a significant advance in functionality over current sync multi-ports, which have no such capability. in addition to this functionality the idt70t3539m sustains the key features of bandwidth and flexibility. the collision detection function is very useful in the case of bursting data, or a string of accesses made to sequential addresses, in that it indicates a problem within the burst, giving the user the option of either repeating the burst or continuing to watch the alert flag to see whether the number of collisions increases above an acceptable threshold value. offering this function on chip also allows users to reduce their need for arbitration circuits, typically done in cpld?s or fpga?s. this reduces board space and design complexity, and gives the user more flexibility in developing a solution. same starting address on both ports and one or both ports writing during each access (i.e., imposes a long string of collisions on contiguous clock cycles), the alert flag will be asserted and cleared every other cycle. please refer to the collision detection timing waveform on page 19.
6.42 idt70t3539m high-speed 2.5v 512k x 36 dual-port synchronous static ram industrial and commercial temperature ranges 22 5678 drw 22 idt70t3539m ce 0 ce 1 ce 1 ce 0 ce 0 ce 1 a 19 ce 1 ce 0 v dd v dd idt70t3539m idt70t3539m idt70t3539m control inputs control inputs control inputs control inputs be , r/ w , oe , clk, ads , repeat , cnten figure 4. depth and width expansion with idt70t3539m depth and width expansion the idt70t3539m features dual chip enables (refer to truth table i) in order to facilitate rapid and simple depth expansion with no requirements for external logic. figure 4 illustrates how to control the various chip enables in order to expand two devices in depth. the idt70t3539m can also be used in applications requiring expanded width, as indicated in figure 4. through combining the control signals, the devices can be grouped as necessary to accommodate applications needing 72-bits or wider. register sizes, and system interface parameter tables. specifically, commands for array b must precede those for array a in any jtag operations sent to the idt70t3539m. please reference application note an-411, "jtag testing of multichip modules" for specific instructions on performing jtag testing on the idt70t3539m. an-411 is available at www.idt.com. array a array b tck tms t rst tdi tdoa tdib tdo 5678drw 23 idt70t3539m figure 5. jtag configuration for idt70t3539m jtag functionality and configuration . the idt70t3539m is composed of two independent memory arrays, and thus cannot be treated as a single jtag device in the scan chain. the two arrays (a and b) each have identical characteristics and commands but must be treated as separate entities in jtag operations. please refer to figure 5. jtag signaling must be provided serially to each array and utilize the information provided in the identification register definitions, scan
6.42 idt70t3539m high-speed 2.5v 512k x 36 dual-port synchronous static ram industrial and commercial temperature ranges 23 jtag ac electrical characteristics (1,2,3,4) 70t3539m symbol parameter min. max. units t jcyc jtag clock input period 100 ____ ns t jch jtag clock high 40 ____ ns t jcl jtag clock low 40 ____ ns t jr jtag clock rise time ____ 3 (1) ns t jf jtag clock fall time ____ 3 (1) ns t jrst jtag reset 50 ____ ns t jrsr jtag reset recovery 50 ____ ns t jcd jtag data output ____ 25 ns t jdc jtag data output hold 0 ____ ns t js jtag setup 15 ____ ns t jh jtag hold 15 ____ ns 5678 tbl 15 notes: 1. guaranteed by design. 2. 30pf loading on external output signals. 3. refer to ac electrical test conditions stated earlier in this document. 4. jtag operations occur at one speed (10mhz). the base device may run at any speed specified in this datasheet. jtag timing specifications tck device inputs (1) / tdi/tms d evice outputs (2) / tdo trst t jcd t jdc t jrst t js t jh t jcyc t jrsr t jf t jcl t jr t jch 5678 drw 24 , figure 6. standard jtag timing notes: 1. device inputs = all device inputs except tdi, tms, and trst. 2. device outputs = all device outputs except tdo.
6.42 idt70t3539m high-speed 2.5v 512k x 36 dual-port synchronous static ram industrial and commercial temperature ranges 24 identification register definitions instruction field array b value array b instruction field array a value array a description revision number (31:28) 0x0 revision number (63:60) 0x0 reserved for version number idt device id (27:12) 0x333 idt device id (59:44) 0x333 defines idt part number idt jedec id (11:1) 0x33 idt jedec id (43:33) 0x33 allows unique identification of device vendor as idt id register indicator bit (bit 0) 1 id register indicator bit (bit 32) 1 indicates the presence of an id register 5678 tbl 16 scan register sizes register name bit size array a bit size array b bit size 70t3539m instruction (ir) 4 4 8 bypass (byr) 1 1 2 identification (idr) 32 32 64 boundary scan (bsr) note (3) note (3) note (3) 5678 tbl 17 system interface parameters instruction code description extest 00000000 forces contents of the boundary scan cells onto the device outputs (1) . places the boundary scan register (bsr) between tdi and tdo. bypass 11111111 places the bypass register (byr) between tdi and tdo. idcode 00100010 loads the id register (idr) with the vendor id code and places the register between tdi and tdo. highz 01000100 places the bypass register (byr) between tdi and tdo. forces all device output drivers except int x and col x to a high-z state. clamp 00110011 uses byr. forces contents of the boundary scan cells onto the device outputs. places the bypass register (byr) between tdi and tdo. sample/preload 00010001 places the boundary scan register (bsr) between tdi and tdo. sample allows data from device inputs (2) to be captured in the boundary scan cells and shifted serially through tdo. preload allows data to be input serially into the boundary scan cells via the tdi. reserved 01010101, 01110111, 10001000, 10011001, 10101010, 10111011, 11001100 several combinations are reserved. do not use codes other than those identified above. private 01100110,11101110, 11011101 for internal use only. 5678 tbl 18 notes: 1. device outputs = all device outputs except tdo. 2. device inputs = all device inputs except tdi, tms, and trst . 3. the boundary scan descriptive language (bsdl) file for this device is available on the idt website (www.idt.com), or by conta cting your local idt sales representative.
6.42 idt70t3539m high-speed 2.5v 512k x 36 dual-port synchronous static ram industrial and commercial temperature ranges 25 ordering information a power 999 speed a package a process/ temperature range xxxxx device type blank i bc 166 133 70t3539m s commercial (0c to +70c) industrial (-40c to +85c) 256-pin bga (bc-256) 18mbit (512k x 36) 2.5v synchronous dual-port ram standard power speed in megahertz commercial only commercial & industrial 5678 drw 25 idt idt clock solution for idt70t3539m dual-port idt dual-port part number dual-port i/o specitications clock specifications idt pll clock device idt non-pll clock device vo lta ge i /o input capacitance input duty cycle requirement maximum frequency jitter tol eran ce 70t3539m 3.3/2.5 lvttl 15pf 40% 166 75ps 5t2010 5t9010 5t905, 5t9050 5t907, 5t9070 5678 tbl 19
6.42 idt70t3539m high-speed 2.5v 512k x 36 dual-port synchronous static ram industrial and commercial temperature ranges 26 the idt logo is a registered trademark of integrated device technology, inc. corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 408-284-2794 san jose, ca 95138 fax: 408-284-2775 dualporthelp@idt.com www.idt.com datasheet document history: 10/08/03: initial datasheet 10/20/03: page 1 added "includes j tag functionality" to features page 25 added idt clock solution table 12/04/03: page 10 added t ofs symbol and parameter to ac electrical characteristics table page 19 updated collision timing waveform page 19 added collision detection timing table and footnotes page 22 added jtag configuration and jtag functionality descriptions 02/02/04: page 8 changed i sb 3 and i zz in the dc electrical characteristics table 04/08/04: page 20 & 21 clarified sleep mode text and waveform page 22 added an application note, an-411, reference to the jtag functionality and configuration text page 4 added another sentence to footnote 4 to recommend that boundary scan not be operated during sleep mode 05/28/04: removed "preliminary" status 07/25/08: page 8 corrected a typo in the footnotes of the dc chars table ?

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